Publications (19) LUIS PARRILLA ROURE publications

filter_list Electrical and Electronic Engineering

2024

  1. Towards efficient hardware digital twins of lithium-ion batteries

    2024 39th Conference on Design of Circuits and Integrated Systems, DCIS 2024

2017

  1. Classification algorithms for fetal QRS extraction in abdominal ECG signals

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2015

  1. Design time optimization for hardware watermarking protection of HDL designs

    Scientific World Journal, Vol. 2015

  2. Towards Project-Based Learning applied to the Electronic Engineering Studies

    2015 Conference on Design of Circuits and Integrated Systems, DCIS 2015

2014

  1. ECG processing on reconfigurable hardware for efficient artifact reduction

    Experimental and Clinical Cardiology, Vol. 20, Núm. 8, pp. 3023-3028

2011

  1. Intellectual Property Protection (IPP) using obfuscation in C, VHDL, and Verilog coding

    Proceedings of SPIE - The International Society for Optical Engineering

2010

  1. Protection of microprocessor-based cores for FPL devices

    6th Southern Programmable Logic Conference, SPL 2010 - Proceedings

  2. Ring oscillators as thermal sensors in FPGAS: Experiments in low voltage

    6th Southern Programmable Logic Conference, SPL 2010 - Proceedings

2009

  1. Design and performance of an adaptation middleware interface for a civil avionic bus

    AIAA/IEEE Digital Avionics Systems Conference - Proceedings

  2. Enhanced gradient-based motion vector coprocessor

    FPL 09: 19th International Conference on Field Programmable Logic and Applications

  3. New advances for automated IP soft-core watermarking

    Proceedings of SPIE - The International Society for Optical Engineering

2008

  1. Automated signature insertion in combinational logic patterns for HDL IP core protection

    Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL

2007

  1. IPP@HDL: Efficient intellectual property protection scheme for IP cores

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, Núm. 5, pp. 578-591

2006

  1. IPP watermarking technique for IP core protection on FPL devices

    Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

  2. RNS-based watermarking for IP cores

    PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings

2005

  1. Efficient clock distribution scheme for VLSI RNS-enabled controllers

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Watermarking strategies for RNS-based system intellectual property protection

    IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

2000

  1. Implementation of RNS analysis and synthesis filter banks for the orthogonal discrete wavelet transform over FPL devices

    Midwest Symposium on Circuits and Systems

  2. RNS-FPL merged architectures for orthogonal DWT

    Electronics Letters, Vol. 36, Núm. 14, pp. 1198-1199