Publications (34) LUIS PARRILLA ROURE publications

filter_list Hardware and Architecture

2024

  1. Hardware Implementations of a Deep Learning Approach to Optimal Configuration of Reconfigurable Intelligence Surfaces

    Sensors, Vol. 24, Núm. 3

2023

  1. Digital Implementation of Radial Basis Function Neural Networks Based on Stochastic Computing

    IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 13, Núm. 1, pp. 257-269

  2. Revisiting Multiple Ring Oscillator-Based True Random Generators to Achieve Compact Implementations on FPGAs for Cryptographic Applications

    Cryptography, Vol. 7, Núm. 2

2022

  1. Dracon: An Open-Hardware Based Platform for Single-Chip Low-Cost Reconfigurable IoT Devices

    Electronics (Switzerland), Vol. 11, Núm. 13

  2. Table-Free Seed Generation for Hardware Newton-Raphson Square Root and Inverse Square Root Implementations in IoT Devices

    IEEE Internet of Things Journal, Vol. 9, Núm. 9, pp. 6985-6995

  3. Time- and Amplitude-Controlled Power Noise Generator against SPA Attacks for FPGA-Based IoT Devices

    Journal of Low Power Electronics and Applications, Vol. 12, Núm. 3

2019

  1. Efficient Elliptic Curve Cryptoprocessor for enabling TLS protocol in low-cost reconfigurable SoCs

    2019 34th Conference on Design of Circuits and Integrated Systems, DCIS 2019

  2. Efficient implementation on low-cost SoC-FPGAs of TLSv1.2 protocol with ECC_AES support for secure IoT coordinators

    Electronics (Switzerland), Vol. 8, Núm. 11

  3. Elliptic Curve Cryptography hardware accelerator for high-performance secure servers

    Journal of Supercomputing, Vol. 75, Núm. 3, pp. 1107-1122

2017

  1. A new area-efficient BCD-digit multiplier

    Digital Signal Processing: A Review Journal, Vol. 62, pp. 1-10

2016

  1. Comments on “Fast architecture for decimal digit multiplication”

    Microprocessors and Microsystems, Vol. 47, pp. 441-444

2015

  1. Hardware implementation of a new ECC key distribution protocol for securing Wireless Sensor Networks

    2015 Conference on Design of Circuits and Integrated Systems, DCIS 2015

2012

  1. Minimum-clock-cycle Itoh-Tsujii algorithm hardware implementation for cryptography applications over GF(2 m) fields

    Electronics Letters, Vol. 48, Núm. 18, pp. 1126-1128

2010

  1. Protection of microprocessor-based cores for FPL devices

    6th Southern Programmable Logic Conference, SPL 2010 - Proceedings

2008

  1. FPGA based architecture for robust optical flow computation

    Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL

  2. Intellectual property protection of IP cores at HDL design level with automatic signature spreading

    Proceedings - International Conference on Advances in Electronics and Micro-electronics, ENICS 2008

2007

  1. Digital signature embedding technique for IP core protection

    Proceedings - 2007 3rd Southern Conference on Programmable Logic, SPL'07

  2. IPP@HDL: Efficient intellectual property protection scheme for IP cores

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, Núm. 5, pp. 578-591

  3. Intellectual property protection of HDL IP cores through automated signature hosting

    Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

  4. Intellectual property protection of IP cores through high-level watermarking

    Proceedings of SPIE - The International Society for Optical Engineering