Optimization of the Z2-Fet memory cell for future technologies

Resumen

The aim of the work presented in this thesis is the characterization of thin-oxide Z2-FET devices as DRAM (Dynamic Random Access Memory) cells. The DRAM evolution has been supported by the memory cell down-scaling. The traditional DRAM cell consists of one transistor and one capacitor (1T-1C), hence its miniaturization relies in reducing both component footprints. The feasibility of this process for future memory nodes is now questioned due to the increasing difficulties that the capacitor down-scaling imposes: there exists a technology-independent minimum capacitance that prevents further scaling. Novel approaches have been proposed to solve this issue, among which the capacitor-less cells are a serious candidate. These devices are composed by a single SOI (Silicon-On-Insulator) transistor (1T) that exploits the SOI floating-body effect to effectively confine the charge in the body of the transistor rather than in an external capacitor. This allows to remove the traditional cell capacitor, so 1T-DRAM cells can be further scaled in the same manner as conventional SOI transistors are. By controlling the charge injection/evacuation in the body of 1T-DRAM cells, a threshold voltage shift is induced which, for fixed reading conditions, modulates the drain current enabling two distinct levels associated to each logic state. To inject/evacuate charge in the transistor body, several mechanisms exist such as band to band tunneling and capacitive coupling. This work is focused on the Z2-FET cell characterization for different cell geometries. Initially, the principle of operation of this cell, besides some of the most relevant characteristics is explained. This includes the outstanding sharp current switch and hysteresis effects. The characterization of the Z2-FET 1T-DRAM cell is accomplished at different levels. Firstly, the DC characterization is performed, extracting the gate biasing conditions that exhibit the sharp current onset, corresponding anode current, and how this parameter is affected by gate biasing and geometry. Then, the memory effect is validated by characterizing the most relevant metrics: current margin, current ratio, memory window and retention time. As a further step to assess the Z2-FET potential, a 2x2 memory matrix is experimentally demonstrated. The basic architecture is explained, as well as some variants, to later undertake the measurements at different levels: single-cell, word and whole-matrix access are successfully demonstrated, proving the correct logic-state storage and later recovery. Disturbance tests are also verified. The reliability of the Z2-FET cell is also studied. BTI (Bias Temperature Instabilities), TDDB (Time-Dependent Dielectric Breakdown) and front-gate tunneling characterizations are analyzed. On the one side, BTI reveals the dynamics of the dielectric at stressing conditions. On the other side, the modulation of the anode voltage at which the sharp current switch is triggered is also studied. Regarding the TDDB analysis, a trade-off between variability and reliability is observed, suggesting that both parameters cannot be optimized independently. To finish this study, the front-gate tunneling current is demonstrated to worsen some memory parameters, being trap-assisted tunneling the major mechanism that rules this current. Finally, the experimental characterization of the first III-V MSDRAM cell to date has been accomplished. The main DC characteristics and memory parameters are successfully extracted demonstrating the correct behavior and future potential of these materials for memory applications.