Implementation of the Pipeline Parallel Programming Technique as an HLPCUsage, Usefulness and Performance

  1. Rossainz-Lopez, Mario 1
  2. Capel-Tuñon, Manuel I. 2
  3. Carrasco-Limón, Odón 1
  4. Hernández-Polo, Fernando 1
  5. Sánchez-Rinza, Bárbara 1
  1. 1 Benemérita Universidad Autónoma de Puebla
    info

    Benemérita Universidad Autónoma de Puebla

    Heróica Puebla de Zaragoza, México

    ROR https://ror.org/03p2z7827

  2. 2 Universidad de Granada
    info

    Universidad de Granada

    Granada, España

    ROR https://ror.org/04njjy449

Revista:
Annals of Multicore and GPU Programming: AMGP

ISSN: 2341-3158

Año de publicación: 2017

Volumen: 4

Número: 1

Páginas: 9-22

Tipo: Artículo

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Otras publicaciones en: Annals of Multicore and GPU Programming: AMGP

Resumen

This article presents the pipeline communication/interaction pattern for concurrent, parallel and distributed systems as a high-level parallel composition (HLPC) and discusses its usefulness for deriving parallel versions of sequential algorithms. In particular, we provide examples of the parallel solution for the following problems: adding numbers, sorting numbers and solving a system of linear equations. An approach based on structured parallelism and the parallel object concept is used to solve these problems. In its generic pattern, the pipeline pattern is shown as an HLPC that deploys three types of parallel objects (a manager, various stages and a collector) which are interconnected to form the pipeline processing structure. We also use a method to systematically create the HLPC pipeline and solve this type of problem. Each pipeline instance must be able to handle predefined synchronization restrictions between processes (maximum parallelism, mutual exclusion and synchronization of the producer-consumer type, the use of synchronous, asynchronous and future asynchronous communication, etc.). Finally, the article presents the performance of pipeline HLPC-based implementations of parallel algorithms for solving the problems raised in the paper by using exclusive CPUs.

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