Real-time visual saliency architecture for FPGA with top-down attention modulation

  1. Barranco, F.
  2. Diaz, J.
  3. Pino, B.
  4. Ros, E.
Revue:
IEEE Transactions on Industrial Informatics

ISSN: 1551-3203

Année de publication: 2014

Volumen: 10

Número: 3

Pages: 1726-1735

Type: Article

DOI: 10.1109/TII.2014.2319581 GOOGLE SCHOLAR
La source de données: Scopus