DITEC - TECNICAS DIGITALES
DITEC - TECNICAS DIGITALES
ANTONIO
LLORÍS RUIZ
Investigador no período 2017-2018
Publicacións nas que colabora con ANTONIO LLORÍS RUIZ (56)
2022
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Table-Free Seed Generation for Hardware Newton-Raphson Square Root and Inverse Square Root Implementations in IoT Devices
IEEE Internet of Things Journal, Vol. 9, Núm. 9, pp. 6985-6995
2017
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A new area-efficient BCD-digit multiplier
Digital Signal Processing: A Review Journal, Vol. 62, pp. 1-10
2016
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Comments on “Fast architecture for decimal digit multiplication”
Microprocessors and Microsystems, Vol. 47, pp. 441-444
2014
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Algebraic circuits
Intelligent Systems Reference Library, Vol. 66, pp. iii-v
2012
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Minimum-clock-cycle Itoh-Tsujii algorithm hardware implementation for cryptography applications over GF(2 m) fields
Electronics Letters, Vol. 48, Núm. 18, pp. 1126-1128
2010
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Protection of microprocessor-based cores for FPL devices
6th Southern Programmable Logic Conference, SPL 2010 - Proceedings
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Watermarking strategies for IP protection of micro-processor cores
Proceedings of SPIE - The International Society for Optical Engineering
2009
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New advances for automated IP soft-core watermarking
Proceedings of SPIE - The International Society for Optical Engineering
2008
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Automated signature insertion in combinational logic patterns for HDL IP core protection
Proceedings - 2008 4th Southern Conference on Programmable Logic, SPL
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HDL-level automated watermarking of IP cores
Proceedings of SPIE - The International Society for Optical Engineering
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Intellectual property protection of IP cores at HDL design level with automatic signature spreading
Proceedings - International Conference on Advances in Electronics and Micro-electronics, ENICS 2008
2007
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Digital signature embedding technique for IP core protection
Proceedings - 2007 3rd Southern Conference on Programmable Logic, SPL'07
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IPP@HDL: Efficient intellectual property protection scheme for IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, Núm. 5, pp. 578-591
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Intellectual property protection of HDL IP cores through automated signature hosting
Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
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Intellectual property protection of IP cores through high-level watermarking
Proceedings of SPIE - The International Society for Optical Engineering
2006
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RNS-based watermarking for IP cores
PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings
2005
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Efficient clock distribution scheme for VLSI RNS-enabled controllers
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Efficient embedded FPL resource usage for RNS-based polyphase DWT filter banks
Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL
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Watermarking strategies for RNS-based system intellectual property protection
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
2004
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Intellectual property protection for RNS circuits on FPGAs
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)