FRANCISCO JOSÉ
PELAYO VALLE
CATEDRÁTICO DE UNIVERSIDAD
Universidad Complutense de Madrid
Madrid, EspañaPublikationen in Zusammenarbeit mit Forschern von Universidad Complutense de Madrid (2)
1998
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Focal-Plane and Multiple Chip VLSI Approaches to CNNs
Analog Integrated Circuits and Signal Processing, Vol. 15, Núm. 3, pp. 263-275
1997
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VLSI Implementation of a Neural Model Using Spikes
Analog Integrated Circuits and Signal Processing, Vol. 13, Núm. 1-2, pp. 111-121