ANTONIO
GARCÍA RÍOS
CATEDRÁTICO DE UNIVERSIDAD
Universidad de Jaén
Jaén, EspañaPublicaciones en colaboración con investigadores/as de Universidad de Jaén (12)
2006
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Pre-processor for bioinspired optical flow models: A customizable hardware implementation
Proceedings of the Mediterranean Electrotechnical Conference - MELECON
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Pre-processor for bioinspired optical flow models: A customizable hardware implementation.
CIRCUITS AND SYSTEMS FOR SIGNAL PROCESSING , INFORMATION AND COMMUNICATION TECHNOLOGIES, AND POWER SOURCES AND SYSTEMS, VOL 1 AND 2, PROCEEDINGS
2001
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Design of RNS-based distributed arithmetic DWT filterbanks
ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, Vol. 2, pp. 1193-1196
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Implementation of the One Dimensional Discrete Cosine Transform using the Residue Number System
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
2000
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A RNS-based matrix-vector-multiply FCT architecture for DCT computation
Midwest Symposium on Circuits and Systems, Vol. 1, pp. 350-353
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A new RNS architecture for the computation of the scaled 2D-DCT on field-programmable logic
Conference Record of the Asilomar Conference on Signals, Systems and Computers, Vol. 1, pp. 379-383
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An efficient RNS architecture for the computation of discrete wavelet transforms on programmable devices
European Signal Processing Conference
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Analysis of RNS-FPL synergy for high throughput DSP applications: Discrete wavelet transform
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Fast RNS-based 2D-DCT computation on field-programmable devices
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, pp. 365-373
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RNS-FPL merged architectures for orthogonal DWT
Electronics Letters, Vol. 36, Núm. 14, pp. 1198-1199
1999
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A new implementation of the discrete cosine transform in the residue number system
Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers
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A novel RNS-based SIMD RISC processor for digital signal processing
Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers