ANTONIO
GARCÍA RÍOS
CATEDRÁTICO DE UNIVERSIDAD
Universidad Autónoma de Madrid
Madrid, EspañaUniversidad Autónoma de Madrid-ko ikertzaileekin lankidetzan egindako argitalpenak (6)
2010
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Protection of microprocessor-based cores for FPL devices
6th Southern Programmable Logic Conference, SPL 2010 - Proceedings
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Watermarking strategies for IP protection of micro-processor cores
Proceedings of SPIE - The International Society for Optical Engineering
2002
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RNS-enabled digital signal processor design
Electronics Letters, Vol. 38, Núm. 6, pp. 266-268
2001
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Implementation of a communications using FPGAs and RNS arithmetic
Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 28, Núm. 1-2, pp. 115-128
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Implementation of the One Dimensional Discrete Cosine Transform using the Residue Number System
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
2000
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A new RNS architecture for the computation of the scaled 2D-DCT on field-programmable logic
Conference Record of the Asilomar Conference on Signals, Systems and Computers, Vol. 1, pp. 379-383