JAVIER
RAMÍREZ PÉREZ DE INESTROSA
CATEDRÁTICO DE UNIVERSIDAD
ANTONIO
LLORÍS RUIZ
Investigador en el periodo 2017-2018
Publicaciones en las que colabora con ANTONIO LLORÍS RUIZ (25)
2005
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Efficient embedded FPL resource usage for RNS-based polyphase DWT filter banks
Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL
2003
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Design and implementation of RNS-based adaptive filters
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2778, pp. 1135-1138
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Design and implementation of high-performance RNS wavelet processors using custom IC technologies
Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 34, Núm. 3, pp. 227-237
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Implementation of RNS-based distributed arithmetic discrete wavelet transform architectures using field-programmable logic
Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 33, Núm. 1-2, pp. 171-190
2002
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A new methodology for efficient synchronization of RNS-based VLSI systems
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Clock distribution in RNS-based VLSI systems
Advances in Systems Engineering, Signal Processing and Communications, pp. 323-328
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Controladores PID adaptativos basados en el sistema numérico de residuos
SAAEI'02: IX Seminario Anual de Automática, Electrónica Industrial e Instrumentación, Universidad de Alcalá, Alcalá de Henares, 18, 19 y 20 de septiembre de 2002
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Fast RNS FPL-based communications receiver design and implementation
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Implementación de bancos de filtros ortogonales de alta velocidad por medio del RNS
SAAEI'02: IX Seminario Anual de Automática, Electrónica Industrial e Instrumentación, Universidad de Alcalá, Alcalá de Henares, 18, 19 y 20 de septiembre de 2002
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RNS-enabled digital signal processor design
Electronics Letters, Vol. 38, Núm. 6, pp. 266-268
2001
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Design of RNS-based distributed arithmetic DWT filterbanks
ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, Vol. 2, pp. 1193-1196
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Implementation of the One Dimensional Discrete Cosine Transform using the Residue Number System
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
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Index-based RNS DWT architectures for custom IC designs
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
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Instrumentos, métodos y equipos de medida
Granada (Campus de Fuentenueva, s/n, 18071 Granada) : P. García Fernández, 2001
2000
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A RNS-based matrix-vector-multiply FCT architecture for DCT computation
Midwest Symposium on Circuits and Systems, Vol. 1, pp. 350-353
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A new RNS architecture for the computation of the scaled 2D-DCT on field-programmable logic
Conference Record of the Asilomar Conference on Signals, Systems and Computers, Vol. 1, pp. 379-383
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An efficient RNS architecture for the computation of discrete wavelet transforms on programmable devices
European Signal Processing Conference
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Analysis of RNS-FPL synergy for high throughput DSP applications: Discrete wavelet transform
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Fast RNS-based 2D-DCT computation on field-programmable devices
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, pp. 365-373
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Implementation of RNS analysis and synthesis filter banks for the orthogonal discrete wavelet transform over FPL devices
Midwest Symposium on Circuits and Systems