Publicaciones en las que colabora con FRANCISCO JOSÉ PELAYO VALLE (11)

2002

  1. Parameter configurations for hole extraction in cellular neural networks (CNN)

    Analog Integrated Circuits and Signal Processing, Vol. 32, Núm. 2, pp. 149-155

1999

  1. Implementation of adaptable and hierarchical fuzzy T-norm

    Electronics Letters, Vol. 35, Núm. 24, pp. 2150-2152

  2. New methodology for the development of adaptive and self-learning fuzzy controllers in real time

    International Journal of Approximate Reasoning, Vol. 21, Núm. 2, pp. 109-136

1998

  1. Focal-Plane and Multiple Chip VLSI Approaches to CNNs

    Analog Integrated Circuits and Signal Processing, Vol. 15, Núm. 3, pp. 263-275

1997

  1. A low-power cmos implementation of programmable cnn's with embedded photosensors

    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 44, Núm. 2, pp. 149-153

1996

  1. VLSI implementations of CNNs for image processing and vision tasks: single and multiple chip approaches

    Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications

1995

  1. A low-power analog implementation of cellular neural networks

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

1994

  1. Continuous-time analog defuzzifier for product-sum based implementations

    Proceedings of the 4th International Conference on Microelectronics for Neural Networks and Fuzzy Systems, ICMNN 1994

1993

  1. Analog CMOS Implementation of a Discrete Time CNN With Programmable Cloning Templates

    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 40, Núm. 3, pp. 215-218

1991

  1. CMOS implementation of a cellular neural network with dynamically alterable cloning templates

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Red neuronal celular CMOS en modo de corriente con matrices de ponderación dinámicamente modificables

    Diseño de circuitos integrados: actas del VI Congreso. Santander, 11/15 de noviembre de 1991