2010

1. A novel architecture for a massively parallel low level vision processing engine on chip

   IEEE International Symposium on Industrial Electronics

2. High-performance optical-flow architecture based on a multi-scale, multi-orientation phase-based model

   IEEE Transactions on Circuits and Systems for Video Technology, Vol. 20, Núm. 12, pp. 1797-1807

3. Multi-port abstraction layer for FPGA intensive memory exploitation applications

   Journal of Systems Architecture, Vol. 56, Núm. 9, pp. 442-451