Publicaciones en las que colabora con LUIS PARRILLA ROURE (15)

2024

  1. Hardware Implementations of a Deep Learning Approach to Optimal Configuration of Reconfigurable Intelligence Surfaces

    Sensors, Vol. 24, Núm. 3

2002

  1. A new methodology for efficient synchronization of RNS-based VLSI systems

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Clock distribution in RNS-based VLSI systems

    Advances in Systems Engineering, Signal Processing and Communications, pp. 323-328

  3. Controladores PID adaptativos basados en el sistema numérico de residuos

    SAAEI'02: IX Seminario Anual de Automática, Electrónica Industrial e Instrumentación, Universidad de Alcalá, Alcalá de Henares, 18, 19 y 20 de septiembre de 2002

  4. Implementación de bancos de filtros ortogonales de alta velocidad por medio del RNS

    SAAEI'02: IX Seminario Anual de Automática, Electrónica Industrial e Instrumentación, Universidad de Alcalá, Alcalá de Henares, 18, 19 y 20 de septiembre de 2002

2001

  1. Implementation of the One Dimensional Discrete Cosine Transform using the Residue Number System

    Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

2000

  1. A RNS-based matrix-vector-multiply FCT architecture for DCT computation

    Midwest Symposium on Circuits and Systems, Vol. 1, pp. 350-353

  2. A new RNS architecture for the computation of the scaled 2D-DCT on field-programmable logic

    Conference Record of the Asilomar Conference on Signals, Systems and Computers, Vol. 1, pp. 379-383

  3. Analysis of RNS-FPL synergy for high throughput DSP applications: Discrete wavelet transform

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  4. Implementation of RNS analysis and synthesis filter banks for the orthogonal discrete wavelet transform over FPL devices

    Midwest Symposium on Circuits and Systems

  5. Implementation of canonical and retimed RNS architectures for the orthogonal 1-D DWT over FPL devices

    Conference Record of the Asilomar Conference on Signals, Systems and Computers

  6. New architecture to compute the Discrete Cosine Transform using the Quadratic Residue Number System

    Proceedings - IEEE International Symposium on Circuits and Systems

  7. RNS-FPL merged architectures for orthogonal DWT

    Electronics Letters, Vol. 36, Núm. 14, pp. 1198-1199

1999

  1. A new implementation of the discrete cosine transform in the residue number system

    Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers

  2. A novel RNS-based SIMD RISC processor for digital signal processing

    Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers