Publications dans lesquelles il/elle collabore avec ANTONIO LLORÍS RUIZ (13)

1993

  1. Generalized Hopfield Neural Network for Concurrent Testing

    IEEE Transactions on Computers, Vol. 42, Núm. 8, pp. 898-912

  2. Test-Pattern Generation Based on Reed-Muller Coefficients

    IEEE Transactions on Computers, Vol. 42, Núm. 8, pp. 968-980

1991

  1. Aplicación del espectro de Reed-Muller a la generación de patrones de test

    Diseño de circuitos integrados: actas del VI Congreso. Santander, 11/15 de noviembre de 1991

  2. CMOS current-mode multivalued PLA's

    IEEE transactions on circuits and systems, Vol. 38, Núm. 4, pp. 434-441

  3. Characterization and design of hybrid-mode CMOS circuits

    International Journal of Electronics, Vol. 71, Núm. 4, pp. 591-607

  4. Implementation and applications of multivalued decoders

    International Journal of Electronics, Vol. 70, Núm. 4, pp. 785-794

  5. Optimization problems on concurrent testing solved by neural networks

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  6. Universal Built-In Self-Test Procedure for CMOS PLA’s

    IEEE Transactions on Circuits and Systems, Vol. 38, Núm. 8, pp. 941-945

  7. Using reed-muller coefficients to synthesise optimal prediction modules for concurrent testing

    Electronics Letters, Vol. 27, Núm. 14, pp. 1243-1245

1989

  1. Some improvements in the implementation of multithreshold and multivalued I2.L circuits

    International Journal of Electronics, Vol. 66, Núm. 1, pp. 19-34

1988

  1. Design of decoders for Q-valued logic circuits.

    Proceedings of The International Symposium on Multiple-Valued Logic

1985

  1. Multithreshold logic circuits implemented with operational amplifiers

    International Journal of Electronics, Vol. 58, Núm. 3, pp. 395-406

1984

  1. Emulador y ensamblador de un ordenador didáctico elemental

    Revista de informática y automática, Año 17, Núm. 61, pp. 9-18