FRANCISCO JAVIER
GARCÍA RUIZ
CATEDRÁTICO DE UNIVERSIDAD
![Foto de FRANCISCO JAVIER](/img/nophoto.png)
![Foto de Indian Institute of Technology Gandhinagar](/img/noimage_org.png)
Indian Institute of Technology Gandhinagar
Ghandinagar, IndiaPublikationen in Zusammenarbeit mit Forschern von Indian Institute of Technology Gandhinagar (7)
2021
-
A unified compact model for electrostatics of III–V GAA transistors with different geometries
Journal of Computational Electronics, Vol. 20, Núm. 5, pp. 1676-1684
2020
-
Significance of L-valley charges and a method to include it in electrostatic model of III-V GAA FETs
4th Electron Devices Technology and Manufacturing Conference, EDTM 2020 - Proceedings
2019
-
A Compact Charge and Surface Potential Model for III-V Cylindrical Nanowire Transistors
IEEE Transactions on Electron Devices, Vol. 66, Núm. 1, pp. 73-79
-
A compact model for III–V nanowire electrostatics including band non-parabolicity
Journal of Computational Electronics, Vol. 18, Núm. 4, pp. 1229-1235
-
Charge and Capacitance Compact Model for III-V Quadruple-Gate FETs with Square Geometry
2019 IEEE International Conference on Modeling of Systems Circuits and Devices, MOS-AK India 2019
2018
-
Computationally efficient analytic charge model for III-V cylindrical nanowire transistors
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018
2017
-
Modeling of Quantum Confinement and Capacitance in III-V Gate-All-Around 1-D Transistors
IEEE Transactions on Electron Devices, Vol. 64, Núm. 12, pp. 4889-4896