Publicaciones en las que colabora con FRANCISCO BARRANCO EXPÓSITO (17)

2015

  1. Hierarchical architecture for motion and depth estimations based on color cues

    Journal of Real-Time Image Processing, Vol. 10, Núm. 2, pp. 435-452

2014

  1. On-chip semidense representation map for dense visual features driven by attention processes

    Journal of Real-Time Image Processing, Vol. 9, Núm. 1, pp. 171-185

  2. Real-time visual saliency architecture for FPGA with top-down attention modulation

    IEEE Transactions on Industrial Informatics, Vol. 10, Núm. 3, pp. 1726-1735

2013

  1. Pipelined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs

    Digital Signal Processing: A Review Journal, Vol. 23, Núm. 2, pp. 675-688

2012

  1. A multi-resolution approach for massively-parallel hardware-friendly optical flow estimation

    Journal of Visual Communication and Image Representation, Vol. 23, Núm. 8, pp. 1272-1283

  2. Bottom-up visual attention model based on FPGA

    2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012

  3. Parallel architecture for hierarchical optical flow estimation based on FPGA

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, Núm. 6, pp. 1058-1067

  4. Real-time architecture for a robust multi-scale stereo engine on FPGA

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, Núm. 12, pp. 2208-2219

  5. Vector disparity sensor with vergence control for active vision systems

    Sensors, Vol. 12, Núm. 2, pp. 1771-1799

2011

  1. Hierarchical optical flow estimation architecture using color cues

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2010

  1. A novel architecture for a massively parallel low level vision processing engine on chip

    IEEE International Symposium on Industrial Electronics

  2. A novel architecture for a massively parallel low level vision processing engine on chip

    IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (ISIE 2010)

  3. Fine grain pipeline architecture for high performance phase-based optical flow computation

    Journal of Systems Architecture, Vol. 56, Núm. 11, pp. 577-587

  4. High-performance optical-flow architecture based on a multi-scale, multi-orientation phase-based model

    IEEE Transactions on Circuits and Systems for Video Technology, Vol. 20, Núm. 12, pp. 1797-1807

2009

  1. Arquitectura multiescala de cálculo de flujo óptico basado en la fase

    Actas de las IX Jornadas de computación reconfigurable y aplicaciones: Universidad de Alcalá, Departamento de Electrónica, Alcalá de Henares, 9-11 septiembre, 2009

  2. Entorno software para visualización y configuración de procesamiento de imágenes en tiempo real con plataformas reconfigurables

    Actas de las IX Jornadas de computación reconfigurable y aplicaciones: Universidad de Alcalá, Departamento de Electrónica, Alcalá de Henares, 9-11 septiembre, 2009

  3. Visual system based on artificial retina for motion detection

    IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics, Vol. 39, Núm. 3, pp. 752-762