JOSÉ LUIS
PADILLA DE LA TORRE
PROFESOR TITULAR DE UNIVERSIDAD
Università di Udine
Udine, ItaliaPublicaciones en colaboración con investigadores/as de Università di Udine (8)
2017
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A novel reconfigurable sub-0.25-V digital logic family using the electron-hole bilayer TFET
IEEE Journal of the Electron Devices Society, Vol. 6, Núm. 1, pp. 2-7
2016
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Impact of device geometry of the fin Electron-Hole Bilayer Tunnel FET
European Solid-State Device Research Conference
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The Electron-Hole Bilayer TFET: Dimensionality Effects and Optimization
IEEE Transactions on Electron Devices, Vol. 63, Núm. 6, pp. 2603-2609
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Underlap counterdoping as an efficient means to suppress lateral leakage in the electron-hole bilayer tunnel FET
Semiconductor Science and Technology, Vol. 31, Núm. 4
2015
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Efficient quantum mechanical simulation of band-to-band tunneling
EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
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Modeling the imaginary branch in III-V tunneling devices: Effective mass vs k · p
International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
2014
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Electron-hole bilayer deep subthermal electronic switch: Physics, promise and challenges
2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
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Two dimensional quantum mechanical simulation of low dimensional tunneling devices
European Solid-State Device Research Conference