Publicaciones en las que colabora con FRANCISCO JOSÉ PELAYO VALLE (21)

2005

  1. Segmentación del cauce del computador didáctico elemental CODE-2

    Actas de las XVI Jornadas de Paralelismo. [JP'2005]

2002

  1. Time series analysis using normalized PG-RBF network with regression weights

    Neurocomputing, Vol. 42, Núm. 1-4, pp. 267-285

1999

  1. Design and evaluation of a reconfigurable digital architecture for self-organizing maps

    Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999

  2. Statistical analysis of the main parameters in the fuzzy inference process

    Fuzzy Sets and Systems, Vol. 102, Núm. 2, pp. 157-173

1993

  1. A learning algorithm to obtain self-organizing maps using fixed neighbourhood Kohonen networks

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Analog CMOS Implementation of a Discrete Time CNN With Programmable Cloning Templates

    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 40, Núm. 3, pp. 215-218

  3. Current-mode analogue defuzzifier

    Electronics Letters, Vol. 29, Núm. 9, pp. 743-744

  4. Generalized Hopfield Neural Network for Concurrent Testing

    IEEE Transactions on Computers, Vol. 42, Núm. 8, pp. 898-912

  5. MapA: An array processor architecture for neural networks

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  6. Test-Pattern Generation Based on Reed-Muller Coefficients

    IEEE Transactions on Computers, Vol. 42, Núm. 8, pp. 968-980

1991

  1. An approach to isolated word recognition using multilayer perceptrons

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Aplicación del espectro de Reed-Muller a la generación de patrones de test

    Diseño de circuitos integrados: actas del VI Congreso. Santander, 11/15 de noviembre de 1991

  3. CMOS current-mode multivalued PLA's

    IEEE transactions on circuits and systems, Vol. 38, Núm. 4, pp. 434-441

  4. CMOS implementation of a cellular neural network with dynamically alterable cloning templates

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  5. CMOS implementation of synapse matrices with programmable analog weights

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  6. Optimization problems on concurrent testing solved by neural networks

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  7. Red neuronal celular CMOS en modo de corriente con matrices de ponderación dinámicamente modificables

    Diseño de circuitos integrados: actas del VI Congreso. Santander, 11/15 de noviembre de 1991

  8. Universal Built-In Self-Test Procedure for CMOS PLA’s

    IEEE Transactions on Circuits and Systems, Vol. 38, Núm. 8, pp. 941-945