Publicaciones en las que colabora con ANTONIO JAVIER DÍAZ ALONSO (72)

2022

  1. An Efficient Timing System for IFMIF-DONES Facility Based on Ethernet Time Transfer Protocols

    2022 Joint Conference of the European Frequency and Time Forum and IEEE International Frequency Control Symposium, EFTF/IFCS 2022 - Proceedings

2021

  1. Enhancing White Rabbit Synchronization Stability and Scalability Using P2P Transparent and Hybrid Clocks

    IEEE Transactions on Industrial Informatics, Vol. 17, Núm. 11, pp. 7316-7324

  2. Implementation of a Time-Sensitive Networking (TSN) Ethernet Bus for Microlaunchers

    IEEE Transactions on Aerospace and Electronic Systems, Vol. 57, Núm. 5, pp. 2743-2758

  3. Precise Network Time Monitoring: Picosecond-Level Packet Timestamping for Fintech Networks

    IEEE Access, Vol. 9, pp. 40274-40285

2017

  1. Linkedclocks for a robust solution of GNSS timing receivers

    2017 32nd General Assembly and Scientific Symposium of the International Union of Radio Science, URSI GASS 2017

  2. Ultra tight relative timing in finance trading

    Proceedings of the Annual Precise Time and Time Interval Systems and Applications Meeting, PTTI

2015

  1. Codebook hardware implementation on FPGA for background subtraction

    Journal of Real-Time Image Processing, Vol. 10, Núm. 1, pp. 43-57

  2. Hierarchical architecture for motion and depth estimations based on color cues

    Journal of Real-Time Image Processing, Vol. 10, Núm. 2, pp. 435-452

2014

  1. Background subtraction model based on color and depth cues

    Machine Vision and Applications, Vol. 25, Núm. 5, pp. 1211-1225

  2. Background subtraction on embedded hardware

    Background Modeling and Foreground Detection for Video Surveillance (CRC Press), pp. 21-1-21-21

  3. Low-cost sensor to detect overtaking based on optical flow

    Machine Vision and Applications, Vol. 25, Núm. 3, pp. 699-711

  4. On-chip semidense representation map for dense visual features driven by attention processes

    Journal of Real-Time Image Processing, Vol. 9, Núm. 1, pp. 171-185

  5. Real-time visual saliency architecture for FPGA with top-down attention modulation

    IEEE Transactions on Industrial Informatics, Vol. 10, Núm. 3, pp. 1726-1735

2013

  1. Background subtraction based on color and depth using active sensors

    Sensors (Basel, Switzerland), Vol. 13, Núm. 7, pp. 8895-8915

  2. Pipelined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs

    Digital Signal Processing: A Review Journal, Vol. 23, Núm. 2, pp. 675-688