FACULTAD DE MEDICINA
Faculté
ANTONIO JAVIER
DÍAZ ALONSO
CATEDRÁTICO DE UNIVERSIDAD
Publications dans lesquelles il/elle collabore avec ANTONIO JAVIER DÍAZ ALONSO (72)
2023
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Ethernet-based timing system for accelerator facilities: The IFMIF-DONES case
Computer Networks, Vol. 233
2022
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An Efficient Timing System for IFMIF-DONES Facility Based on Ethernet Time Transfer Protocols
2022 Joint Conference of the European Frequency and Time Forum and IEEE International Frequency Control Symposium, EFTF/IFCS 2022 - Proceedings
2021
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Enhancing White Rabbit Synchronization Stability and Scalability Using P2P Transparent and Hybrid Clocks
IEEE Transactions on Industrial Informatics, Vol. 17, Núm. 11, pp. 7316-7324
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Implementation of a Time-Sensitive Networking (TSN) Ethernet Bus for Microlaunchers
IEEE Transactions on Aerospace and Electronic Systems, Vol. 57, Núm. 5, pp. 2743-2758
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Precise Network Time Monitoring: Picosecond-Level Packet Timestamping for Fintech Networks
IEEE Access, Vol. 9, pp. 40274-40285
2020
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Digital Electrical Substation Communications Based on Deterministic Time-Sensitive Networking over Ethernet
IEEE Access, Vol. 8, pp. 93621-93634
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IEEE 1588 High Accuracy Default Profile: Applications and Challenges
IEEE Access, Vol. 8, pp. 45211-45220
2018
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White Rabbit: A Deterministic Time Transfer and Frequency Dissemination Technology for Distrihuted Systems
2018 2nd URSI Atlantic Radio Science Meeting, AT-RASC 2018
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White rabbit HSR: A seamless subnanosecond redundant timing system with low-latency data capabilities for the smart grid
IEEE Transactions on Industrial Informatics, Vol. 14, Núm. 8, pp. 3486-3494
2017
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Linkedclocks for a robust solution of GNSS timing receivers
2017 32nd General Assembly and Scientific Symposium of the International Union of Radio Science, URSI GASS 2017
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Ultra tight relative timing in finance trading
Proceedings of the Annual Precise Time and Time Interval Systems and Applications Meeting, PTTI
2015
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Codebook hardware implementation on FPGA for background subtraction
Journal of Real-Time Image Processing, Vol. 10, Núm. 1, pp. 43-57
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Hierarchical architecture for motion and depth estimations based on color cues
Journal of Real-Time Image Processing, Vol. 10, Núm. 2, pp. 435-452
2014
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Background subtraction model based on color and depth cues
Machine Vision and Applications, Vol. 25, Núm. 5, pp. 1211-1225
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Background subtraction on embedded hardware
Background Modeling and Foreground Detection for Video Surveillance (CRC Press), pp. 21-1-21-21
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Low-cost sensor to detect overtaking based on optical flow
Machine Vision and Applications, Vol. 25, Núm. 3, pp. 699-711
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On-chip semidense representation map for dense visual features driven by attention processes
Journal of Real-Time Image Processing, Vol. 9, Núm. 1, pp. 171-185
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Real-time visual saliency architecture for FPGA with top-down attention modulation
IEEE Transactions on Industrial Informatics, Vol. 10, Núm. 3, pp. 1726-1735
2013
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Background subtraction based on color and depth using active sensors
Sensors (Basel, Switzerland), Vol. 13, Núm. 7, pp. 8895-8915
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Pipelined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs
Digital Signal Processing: A Review Journal, Vol. 23, Núm. 2, pp. 675-688