Modeling of Quantum Confinement and Capacitance in III-V Gate-All-Around 1-D Transistors

  1. Ganeriwala, M.D.
  2. Yadav, C.
  3. Ruiz, F.G.
  4. Marin, E.G.
  5. Chauhan, Y.S.
  6. Mohapatra, N.R.
Journal:
IEEE Transactions on Electron Devices

ISSN: 0018-9383

Year of publication: 2017

Volume: 64

Issue: 12

Pages: 4889-4896

Type: Article

DOI: 10.1109/TED.2017.2766693 GOOGLE SCHOLAR
Data source: Scopus