Real-time architecture for a robust multi-scale stereo engine on FPGA

  1. Tomasi, M.
  2. Vanegas, M.
  3. Barranco, F.
  4. Díaz, J.
  5. Ros, E.
Aldizkaria:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

ISSN: 1063-8210

Argitalpen urtea: 2012

Alea: 20

Zenbakia: 12

Orrialdeak: 2208-2219

Mota: Artikulua

DOI: 10.1109/TVLSI.2011.2172007 GOOGLE SCHOLAR
Datuen iturria: Scopus