Publicaciones en las que colabora con PEDRO CARTUJO CASSINELLO (9)

2017

  1. SPICE modeling of RRAM thermal reset transitions for circuit simulation purposes

    2017 Spanish Conference on Electron Devices, CDE 2017

2005

  1. Double gate silicon-on-insulator transistors: N+-n+ gate versus n+-p+ gate configuration

    2005 Spanish Conference on Electron Devices, Proceedings

2004

  1. Image and exchange-correlation effects in double gate silicon-on-insulator transistors

    Microelectronic Engineering

2003

  1. Influence of image force and many-body correction on electron mobility in ultrathin double gate silicon on insulator inversion layers

    Applied Physics Letters, Vol. 83, Núm. 15, pp. 3120-3122

  2. Remote surface roughness scattering in ultrathin-oxide MOSFETs

    European Solid-State Device Research Conference

2002

  1. Coulomb scattering model for ultrathin silicon-on-insulator inversion layers

    Applied Physics Letters, Vol. 80, Núm. 20, pp. 3835-3837

  2. Electron transport in strained Si inversion layers grown on SiGe-on-insulator substrates

    Journal of Applied Physics, Vol. 92, Núm. 1, pp. 288-295

  3. Monte Carlo simulation of electron mobility in silicon-on-insulator structures

    Solid-State Electronics

2001

  1. Electron transport in silicon-on-insulator devices

    Solid-State Electronics, Vol. 45, Núm. 4, pp. 613-620