Publicaciones en las que colabora con FRANCISCO JAVIER GARCÍA RUIZ (25)

2019

  1. A thorough study of Si nanowire FETs with 3D Multi-Subband Ensemble Monte Carlo simulations

    Solid-State Electronics, Vol. 159, pp. 19-25

2018

  1. 3D multi-subband ensemble Monte Carlo simulation of 〈100〉 and 〈110〉 Si nanowire FETs

    2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018

  2. Multi-Subband Ensemble Monte Carlo simulations of scaled GAA MOSFETs

    Solid-State Electronics, Vol. 143, pp. 49-55

2017

  1. Multi-Subband Ensemble Monte Carlo simulations of scaled GAA MOSFETs

    2017 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS 2017)

  2. Multi-subband ensemble Monte Carlo simulations of scaled GAA MOSFETs

    Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings

  3. Three-dimensional Multi-subband Simulation of Scaled FinFETs

    2017 47TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC)

  4. Three-dimensional multi-subband simulation of scaled FinFETs

    European Solid-State Device Research Conference

2015

  1. Multi-Subband Ensemble Monte Carlo simulation of Si nanowire MOSFETs

    International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

2014

  1. 3D multi-subband ensemble Monte Carlo simulator of FinFETs and nanowire transistors

    International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

  2. Influence of alloy disorder scattering on the hole mobility of SiGe nanowires

    Journal of Applied Physics, Vol. 116, Núm. 24

2013

  1. Effect of confined acoustic phonons on the electron mobility of rectangular nanowires

    Applied Physics Letters, Vol. 103, Núm. 16

2011

  1. HOME-MADE SOFTWARE FOR AUTONOMOUS EDUCATION OF MICROWAVE AMPLIFIERS

    2011 4TH INTERNATIONAL CONFERENCE OF EDUCATION, RESEARCH AND INNOVATION (ICERI)

  2. Simulation of the electrostatic and transport properties of 3D-stacked GAA silicon nanowire FETs

    Solid-State Electronics

2010

  1. A model of the gate capacitance of surrounding gate transistors: Comparison with double-gate MOSFETs

    IEEE Transactions on Electron Devices, Vol. 57, Núm. 10, pp. 2477-2483

  2. Effects of deviations in the cross-section of square Nanowires

    2010 14th International Workshop on Computational Electronics, IWCE 2010

2009

  1. Equivalent oxide thickness of trigate SOI MOSFETs with high-κ insulators

    IEEE Transactions on Electron Devices, Vol. 56, Núm. 11, pp. 2711-2719

  2. Monte Carlo simulation of nanoelectronic devices

    Journal of Computational Electronics, Vol. 8, Núm. 3-4, pp. 174-191

  3. Simulation of hole mobility in DGSOI transistors

    ECS Transactions

2008

  1. Accurate modeling of metal/HfO2/Si capacitors

    Journal of Computational Electronics, Vol. 7, Núm. 3, pp. 155-158

  2. Modeling the equivalent oxide thickness of Surrounding Gate SOI devices with high-κ insulators

    Solid-State Electronics, Vol. 52, Núm. 12, pp. 1854-1860