Publicaciones en las que colabora con S. Cristoloveanu (43)

2018

  1. Gate-induced vs. implanted body doping impact on Z2-FET DC operation

    2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

2017

  1. Extended Analysis of the Z2-FET: Operation as Capacitorless eDRAM

    IEEE Transactions on Electron Devices, Vol. 64, Núm. 11, pp. 4486-4491

2015

  1. Experimental developments of A2RAM memory cells on SOI and bulk substrates

    Solid-State Electronics, Vol. 103, pp. 7-14

  2. Special memory mechanisms in SOI devices

    ECS Transactions

2014

  1. A2RAM: Low-power 1T-DRAM memory cells compatible with planar and 3D SOI substrates

    2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014

  2. In situ characterization of bias instability in bare SOI wafers by pseudo-MOSFET technique

    IEEE Transactions on Device and Materials Reliability, Vol. 14, Núm. 3, pp. 878-883

  3. Tri-Dimensional A2-RAM Cell: Entering the Third Dimension

    Engineering Materials (Springer Science and Business Media B.V.), pp. 105-124

2013

  1. A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration

    Solid-State Electronics, Vol. 90, pp. 127-133

  2. A-RAM family: Novel capacitorless 1T-DRAM cells for 22 nm node and beyond

    Nanoscale Semiconductor Memories: Technology and Applications (CRC Press), pp. 157-180

  3. Bias-engineered mobility in advanced FD-SOI MOSFETs

    IEEE Electron Device Letters, Vol. 34, Núm. 7, pp. 840-842

  4. Determination of effective capacitance area for pseudo-MOSFET based characterization of bare soi wafers by split-C(V) measurements

    ECS Transactions

  5. Direct point-contact characterization of Bias instability on bare SOI wafers

    2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013

  6. Effective capacitance area for pseudo-MOSFET characterization of bare SOIWafers by Split-C(V) measurements

    ECS Journal of Solid State Science and Technology, Vol. 2, Núm. 12

  7. Fabrication and validation of A2RAM memory cells on SOI and bulk substrates

    2013 5th IEEE International Memory Workshop, IMW 2013

  8. Getting rid of the DRAM capacitor

    Future Trends in Microelectronics: Frontiers and Innovations (wiley), pp. 59-72

  9. Impact of back-gate biasing on effective field and mobility in ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect-transistors

    Journal of Applied Physics, Vol. 113, Núm. 14

2012

  1. 3D trigate 1T-DRAM memory cell for 2x nm nodes

    2012 4th IEEE International Memory Workshop, IMW 2012

  2. A 20nm low-power triple-gate multibody 1T-DRAM cell

    International Symposium on VLSI Technology, Systems, and Applications, Proceedings

  3. Advanced concepts for floating-body memories

    International Journal of High Speed Electronics and Systems

  4. Experimental demonstration of A2RAM memory cell on SOI

    Proceedings - IEEE International SOI Conference