Publicaciones en las que colabora con CARLOS MÁRQUEZ GONZÁLEZ (17)

2017

  1. Insights on the Body Charging and Noise Generation by Impact Ionization in Fully Depleted SOI MOSFETs

    IEEE Transactions on Electron Devices, Vol. 64, Núm. 12, pp. 5093-5098

  2. Systematic method for electrical characterization of random telegraph noise in MOSFETs

    Solid-State Electronics, Vol. 128, pp. 115-120

2016

  1. Electrical characterization and conductivity optimization of laser reduced graphene oxide on insulator using point-contact methods

    RSC Advances, Vol. 6, Núm. 52, pp. 46231-46237

  2. Electrical characterization of Random Telegraph Noise in Fully-Depleted Silicon-On-Insulator MOSFETs under extended temperature range and back-bias operation

    Solid-State Electronics, Vol. 117, pp. 60-65

  3. Electrical characterization of Random Telegraph Noise in back-biased Ultrathin Silicon-On-Insulator MOSFETs

    2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2016

  4. Scribing Graphene Circuits

    Future Trends in Microelectronics: Journey into the Unknown (Wiley-IEEE Press), pp. 207-216

2015

  1. Determination of ad hoc deposited charge on bare SOI wafers

    EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon

  2. Determination of ad hoc deposited charge on bare SOI wafers

    2015 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS)

  3. Direct characterization of impact ionization current in silicon-on-insulator body-contacted MOSFETs

    ECS Transactions

  4. Experimental developments of A2RAM memory cells on SOI and bulk substrates

    Solid-State Electronics, Vol. 103, pp. 7-14

  5. On the effective mobility extraction by point-contact techniques on silicon-on-insulator substrates

    Journal of Applied Physics, Vol. 117, Núm. 3

2014

  1. A2RAM: Low-power 1T-DRAM memory cells compatible with planar and 3D SOI substrates

    2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014

  2. A2RAM: Low-power 1T-DRAM memory cells compatible with planar and 3D SOI substrates

    2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

  3. In situ characterization of bias instability in bare SOI wafers by pseudo-MOSFET technique

    IEEE Transactions on Device and Materials Reliability, Vol. 14, Núm. 3, pp. 878-883

  4. Tri-Dimensional A2-RAM Cell: Entering the Third Dimension

    Engineering Materials (Springer Science and Business Media B.V.), pp. 105-124

2013

  1. Direct point-contact characterization of Bias instability on bare SOI wafers

    2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013

  2. Fabrication and validation of A2RAM memory cells on SOI and bulk substrates

    2013 5th IEEE International Memory Workshop, IMW 2013