Publikationen, an denen er mitarbeitet FRANCISCO JESÚS GÁMIZ PÉREZ (74)

2011

  1. An inversion-charge analytical model for square gate-all-around MOSFETs

    IEEE Transactions on Electron Devices, Vol. 58, Núm. 9, pp. 2854-2861

  2. Analytical drain current model reproducing advanced transport models in nanoscale double-gate (DG) MOSFETs

    2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011

  3. Compact drain-current model for reproducing advanced transport models in nanoscale double-gate MOSFETs

    Semiconductor Science and Technology, Vol. 26, Núm. 9

  4. In-depth study of quantum effects in SOI DGMOSFETs for different crystallographic orientations

    IEEE Transactions on Electron Devices, Vol. 58, Núm. 12, pp. 4438-4441

2010

  1. An analytical I-V model for surrounding-gate transistors that includes quantum and velocity overshoot effects

    IEEE Transactions on Electron Devices, Vol. 57, Núm. 11, pp. 2925-2933

  2. An analytical model for square GAA MOSFETs including quantum effects

    Solid-State Electronics, Vol. 54, Núm. 11, pp. 1463-1469

  3. Hole transport in DGSOI devices: Orientation and silicon thickness effects

    Solid-State Electronics, Vol. 54, Núm. 2, pp. 191-195

2009

  1. A new inversion charge centroid model for surrounding gate transistors with HfO2 as gate insulator

    Proceedings of the 2009 Spanish Conference on Electron Devices, CDE'09

  2. Monte Carlo simulation of nanoelectronic devices

    Journal of Computational Electronics, Vol. 8, Núm. 3-4, pp. 174-191

2008

  1. A in-depth simulation study of CMOS inverters based on the novel surrounding gate transistors

    Proceedings - International Conference on Advances in Electronics and Micro-electronics, ENICS 2008

  2. Modeling the centroid and the inversion charge in cylindrical surrounding gate MOSFETs, including quantum effects

    IEEE Transactions on Electron Devices, Vol. 55, Núm. 1, pp. 411-416

2005

  1. Double gate silicon-on-insulator transistors: N+-n+ gate versus n+-p+ gate configuration

    2005 Spanish Conference on Electron Devices, Proceedings