Publicaciones en las que colabora con FRANCISCO JESÚS GÁMIZ PÉREZ (74)

2018

  1. Gate-induced vs. implanted body doping impact on Z2-FET DC operation

    2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

2017

  1. Extended Analysis of the Z2-FET: Operation as Capacitorless eDRAM

    IEEE Transactions on Electron Devices, Vol. 64, Núm. 11, pp. 4486-4491

  2. Insights on the Body Charging and Noise Generation by Impact Ionization in Fully Depleted SOI MOSFETs

    IEEE Transactions on Electron Devices, Vol. 64, Núm. 12, pp. 5093-5098

  3. Novel capacitor-less A2RAM memory cells for beyond 22-nm nodes

    VLSI: Circuits for Emerging Applications (CRC Press), pp. 49-63

  4. Systematic method for electrical characterization of random telegraph noise in MOSFETs

    Solid-State Electronics, Vol. 128, pp. 115-120

2016

  1. Electrical characterization and conductivity optimization of laser reduced graphene oxide on insulator using point-contact methods

    RSC Advances, Vol. 6, Núm. 52, pp. 46231-46237

  2. Electrical characterization of Random Telegraph Noise in Fully-Depleted Silicon-On-Insulator MOSFETs under extended temperature range and back-bias operation

    Solid-State Electronics, Vol. 117, pp. 60-65

  3. Electrical characterization of Random Telegraph Noise in back-biased Ultrathin Silicon-On-Insulator MOSFETs

    2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2016

  4. Scribing Graphene Circuits

    Future Trends in Microelectronics: Journey into the Unknown (Wiley-IEEE Press), pp. 207-216

2015

  1. Determination of ad hoc deposited charge on bare SOI wafers

    EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon

  2. Direct characterization of impact ionization current in silicon-on-insulator body-contacted MOSFETs

    ECS Transactions

  3. Experimental developments of A2RAM memory cells on SOI and bulk substrates

    Solid-State Electronics, Vol. 103, pp. 7-14

  4. Special memory mechanisms in SOI devices

    ECS Transactions

2014

  1. A2RAM: Low-power 1T-DRAM memory cells compatible with planar and 3D SOI substrates

    2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014

  2. In situ characterization of bias instability in bare SOI wafers by pseudo-MOSFET technique

    IEEE Transactions on Device and Materials Reliability, Vol. 14, Núm. 3, pp. 878-883

  3. Tri-Dimensional A2-RAM Cell: Entering the Third Dimension

    Engineering Materials (Springer Science and Business Media B.V.), pp. 105-124

2013

  1. A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration

    Solid-State Electronics, Vol. 90, pp. 127-133

  2. A-RAM family: Novel capacitorless 1T-DRAM cells for 22 nm node and beyond

    Nanoscale Semiconductor Memories: Technology and Applications (CRC Press), pp. 157-180

  3. Bias-engineered mobility in advanced FD-SOI MOSFETs

    IEEE Electron Device Letters, Vol. 34, Núm. 7, pp. 840-842

  4. Determination of effective capacitance area for pseudo-MOSFET based characterization of bare soi wafers by split-C(V) measurements

    ECS Transactions